The challenge of small space LED display to chip

Compared with other display technologies, LED display has the advantages of self illumination, excellent color reduction, high refresh rate, power saving and easy maintenance. High brightness and large size through splicing are the decisive factors for the rapid growth of LED display in the past two decades. In the field of large screen outdoor display, no other technology can compete with LED display technology.

 

But in the past, LED display also has its shortcomings, such as the large spacing between the encapsulated lamp beads, resulting in low resolution, which is not suitable for indoor and close-up viewing. In order to improve the resolution, it is necessary to reduce the spacing between the lamp beads, but the size of the lamp beads is reduced. Although it can improve the resolution of the whole screen, the cost will rise rapidly. The high cost affects the large-scale commercial application of small spacing LED display.

 

In recent years, with the help of the efforts of chip and package manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single package devices is getting lower and lower, LED package devices are getting smaller and smaller, the pixel spacing of display screen is getting smaller and smaller, and the resolution is getting higher and higher, which makes the advantages of small spacing LED display screen in indoor large screen display more and more obvious.

 

At present, small spacing LED is mainly used in advertising media, stadiums, stage background, municipal engineering and other fields, and in the field of transportation, broadcasting, military and other fields to continuously explore the market. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, small spacing LED display will continue to expand market share and occupy the market space of DLP rear projection. According to the prediction of Everbright Securities Research Institute, by 2020, the replacement rate of DLP rear projection by small spacing LED screen will reach 70% ~ 80%.

 

The author is engaged in the blue and green LED chip manufacturing industry, engaged in product development for many years. From the perspective of product design and process technology, this paper discusses the requirements of the development of small spacing LED display for the blue-green LED chip, and the possible solutions for the chip end.

 

Requirements of LED chips for small spacing LED display screen

 

As the core of LED display, LED chip plays an important role in the development of small spacing led. The current achievements and future development of small spacing LED display depend on the unremitting efforts of chip end.

 

On the one hand, the indoor display screen point spacing is gradually reduced from the early P4 to P1.5, P1.0, and p0.8 under development. Correspondingly, the size of lamp beads has been reduced from 3535 and 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and even some are developing 0404 sizes.

 

As we all know, the reduction of package lamp bead size will inevitably require the reduction of chip size. At present, the surface area of common blue-green chips for small spacing display screen in the market is about 30mil2, and some chip factories have been mass producing 25mil2 or even 20mil2 chips.

 

On the other hand, with the decrease of chip surface area and single core brightness, a series of problems that affect the display quality have become prominent.

 

The first is the requirement of gray level. Different from outdoor screen, the difficulty of indoor screen is not brightness but gray. At present, the brightness demand of indoor large spacing screen is about 1500 CD / m2-2000 CD / m2, and the brightness of small spacing LED display screen is generally about 600 CD / m2-800 CD / m2, while the best brightness of display screen suitable for long-term attention is about 100 CD / m2-300 CD / m2.

 

At present, one of the problems of small spacing LED screen is "low brightness and low gray". That is, the gray level under low brightness is not enough. In order to achieve "low brightness and high gray", the current scheme of package end is black bracket. Due to the weak reflection of the black bracket on the chip, the chip is required to have enough brightness.

 

Secondly, the problem of display uniformity. Compared with the conventional screen, the smaller the spacing, the darker the first scan, the less bright and the redder, and the less gray uneven. At present, aiming at the problems such as afterglow, first scan and low gray and red, the package end and IC control end have made efforts to effectively alleviate these problems, and the problem of uniform brightness under low gray level has also been alleviated by point by point correction technology. However, as one of the root causes of the problem, the chip side needs more efforts. Specifically, the uniformity of brightness under small current is better, and the consistency of parasitic capacitance is better.

 

The third is reliability. The current industry standard is that the allowable value of LED dead light rate is 1 / 10000, which is obviously not suitable for small spacing LED display. Because of the large pixel density of the small spacing screen and the close viewing distance, if there is one dead light in 10000 screens, the effect is unacceptable. In the future, the dead light rate needs to be controlled at one in 100000 or even one in a million to meet the demand of long-term use.

 

Generally speaking, with the development of small spacing led, the core segments are required to be smaller in size, higher in relative brightness, better in brightness consistency under small current, better in parasitic capacitance consistency and high in reliability.

 

chip end solutions

 

1. Size reduction chip size reduction

 

On the surface, it's the problem of layout design, which seems to be solved by designing smaller layout according to the needs. However, can the reduction of chip size go on indefinitely? The answer is No. There are several reasons that restrict the reduction of chip size:

 

(1) limitation of package processing. In the process of packaging, two factors limit the reduction of chip size. One is the restriction of suction nozzle. The size of the short side of the chip must be larger than the inner diameter of the nozzle. At present, the inner diameter of suction nozzle with cost performance is about 80um. The second is the limitation of welding wire. The first is that the pad, i.e. chip electrode, must be large enough, otherwise the reliability of the welding wire cannot be guaranteed, and the minimum electrode diameter reported in the industry is 45um; the second is that the spacing between the electrodes must be large enough, otherwise the two welding wires will inevitably interfere with each other.

 

(2) the limitation of chip processing. There are two limitations in the process of chip processing. One is the limitation of layout. In addition to the above limitations of package end, electrode size and electrode spacing, the distance between electrode and mesa, trace width and boundary line spacing of different layers have their limitations. The current characteristics of chip, SD process capability and photolithography processing capability determine the specific limits. Generally, the minimum distance from the p electrode to the edge of the chip is limited to more than 14 μ M.

 

The second is the limitation of the ability of crack processing. SD slicing + mechanical chipping process has limits, chip size is too small may not be able to crack. When the wafer diameter increases from 2 inches to 4 inches, or to 6 inches in the future, the difficulty of slicing will increase, that is to say, the chip size that can be processed will increase. Taking 4-inch chip as an example, if the short side length of the chip is less than 90 μ m and the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.

 

Based on the above reasons, the author boldly predicts that when the chip size is reduced to 17mil2, the chip design and processing capacity will be close to the limit, and there will be basically no space for reduction, unless there is a big breakthrough in the chip technology scheme.

 

2. Brightness improvement

 

Brightness enhancement is the eternal theme of chip. The chip factory improves the internal quantum effect by optimizing the epitaxial program and the external quantum effect by adjusting the chip structure.

 

However, on the one hand, the reduction of chip size will inevitably lead to the reduction of light-emitting area and the decrease of chip brightness. On the other hand, the point spacing of the small spacing display screen reduces, and the demand for the brightness of a single chip decreases. There is a complementary relationship between the two, but there should be a bottom line. At present, in order to reduce the cost of chip, the subtraction is mainly done on the structure, which usually pays the price of brightness reduction. Therefore, how to balance the trade-offs is a problem that the industry should pay attention to.

 

3. Consistency at low current

 

The so-called small current is relative to the current of conventional indoor and outdoor chip trial. As shown in the following figure, the I-V curve of the chip. The conventional indoor and outdoor chips work in the linear working area, with large current. The small gap LED chip needs to work in the non-linear working area near the zero point, and the current is relatively small.

 

In the non-linear working area, LED chips are affected by the threshold of semiconductor switch, and the difference between chips is more obvious. It is easy to see that the discreteness of non-linear work area is much greater than that of linear work area by analyzing the discreteness of brightness and wavelength of large quantities of chips. This is the inherent challenge of the chip.

 

The way to deal with this problem is firstly to optimize the epitaxial direction, mainly to reduce the lower limit of the linear working area; secondly, to optimize the chip beam splitting, to distinguish the chips with different characteristics.

 

4. Consistency of parasitic capacitance

 

At present, there is no condition to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and conventional measurement items is not clear, which is to be summarized by the industry. The direction of chip end optimization is to adjust the extension and refine the electrical grading, but the cost is very high, which is not recommended.

 

5. reliability

 

The reliability of chip end can be described by various parameters in the process of chip packaging and aging. But generally speaking, the factors that affect the reliability of the chip after it is put on the screen are mainly ESD and IR.

 

ESD refers to anti-static capability. According to IC industry reports, more than 50% of chip failures are related to ESD. In order to improve the reliability of the chip, ESD capability must be improved. However, under the condition of the same epitaxial chip and the same chip structure, the ESD capability will be weakened when the chip size becomes smaller. This is directly related to the current density and chip capacitance characteristics, which can not be resisted.

 

IR refers to reverse leakage, which is usually measured at a fixed reverse voltage. IR reflects the number of defects inside the chip. The larger the IR value is, the more defects are in the chip.

 

In order to improve ESD capability and IR performance, more optimization must be made in epitaxial structure and chip structure. In the chip grading, through strict grading standards, we can effectively eliminate the chips with weak ESD ability and IR performance, so as to improve the reliability of the chip on the screen.

 

Four, summary

 

To sum up, the author analyzes the series of challenges faced by LED chip with the development of small spacing LED display screen, and gives the improvement plan or direction one by one. It should be said that there is still a lot of room for LED chip optimization. How to improve is still waiting for the employees to exert their intelligence and make continuous efforts.